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description the A8508 is a multi-output white led driver for backlighting lcd panels. it integrates a current-mode boost controller and eight individual current sinks. the boost controller architecture allows for significant scaling of boost voltage to optimize the solution for the required number of leds per string. the fset/sync pin either sets the required boost switching frequency or synchronizes the value in the range of 300 to 800 khz. the led sink current value is set by an external iset resistor (see figure 1). the eight led sinks can also be combined to achieve even higher current per led string. the A8508 provides protection against output shorts and overvoltage, open or shorted led pins, and overtemperature. a dual-level, pulse-by-pulse current limit function provides soft start and protects the external current switch against high current overloads. as an option, the A8508 can drive an external p-fet interfaced to the f a u l t pin to disconnect the input supply from the system in the event of short-to-ground in the boost converter. the A8508 is available in a 24-pin tssop package (suffix lp) with an exposed thermal pad for enhanced thermal dissipation. contact factory for additional options, including: a 24-pin soicw (lw) or a a 5 5 mm 28-contact qfn (et) with exposed thermal pad. all packages are lead (pb) free, with 100% matte tin leadframe plating. A8508-ds, rev. 1 features and benefits ? eight integrated high current sinks for led strings; can be tied together for even higher currents ? fixed frequency current mode control with integrated gate driver / boost controller; powerful gate driver to drive an external n-channel mosfet allows significant scaling capability on the number of leds per string ? parallel operation capability with one boost controller (master) and up to three additional slave controllers; can run up to 32 strings of leds while populating only a single master boost regulator ? active current sharing between led strings for 0.7% accuracy and 0.8% matching ? wide input voltage range: 9 to 40 v ? internal bias supply for single-supply operation (typically v in = 12 or 24 v) ? fset / sync function to either set the boost converter switching frequency or synchronize at up to 800 khz ? protection features ? open or shorted led pin protection ? open schottky protection ? pulse-by-pulse current limit ? overtemperature protection (otp) wide input voltage range, high efficiency 8-channel fault tolerant led driver typical application A8508 packages (not to scale) 24-pin soicw (lw package) 24-pin tssop with exposed thermal pad (lp package) 28-contact qfn with exposed thermal pad (et package) vdd vdr iset fset/sync riset rz cz cdd cdr cp rfset rvdr comp mode led5 led7 agnd pgnd pad en gate vin senn senp ovp cout q1 rovp r sense d1 vout v in v dd c in l1 A8508 led8 led6 led4 led3 led1 led2 pwm r1 fault 5.00 10.00 15.00 20.00 25.00 30.00 30 50 70 90 110 130 150 riset value versus led current i led (ma) r iset (k ) figure 1. typical application circuit showing 8 channels of leds; rz-cz optional (component list shown in the typical applications section)
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings* characteristic symbol notes rating unit ledx pin voltage v ledx ?0.3 to 55 v ovp pin voltage v ovp ?0.3 to 60 v vin pin voltage v in ?0.3 to 40 v f a u l t pin voltage v fault ?0.3 to 40 v comp, en, fset/sync, iset, mode, pwm, senn, senp, and vdd pin voltage ? ?0.3 to 5.5 v gate, vdr pin voltage ? ?0.3 to 8 v operating ambient temperature t a g temperature range ?40 to 105 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc *stresses beyond those listed in this table may cause permanent damage to the device. the absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the elec trical characteristics table is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reli ability. selection guide part number package packing 1 A8508gettr-t 2 28-contact qfn with exposed thermal pad contact factory A8508glptr-t 24-pin tssop with exposed thermal pad 4000 pieces per 13-in. reel A8508glwtr-t 2 24-pin soicw contact factory 1 contact allegro ? for additional packing options. 2 contact factory for availability. thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value unit package thermal resistance r ja package et, on 4-layer pcb based on jedec standard 32 oc/w package lp, on 4-layer pcb based on jedec standard 28 oc/w package lw, on 4-layer pcb based on jedec standard 44 oc/w *additional thermal information available on the allegro website table of contents specifications 2 functional block diagram 3 pin-out diagram and terminal list 4 electrical characteristics table 5 functional description 8 enabling the ic 8 powering up: led pin short-to-gnd check 8 soft start function 9 frequency selection 10 synchronization 10 led current setting and led dimming 11 pwm dimming 12 analog dimming 12 boost switch overcurrent protection 13 setting the current sense resistor 13 current sense resistor routing 13 pulse-by-pulse current limit 14 secondary boost switch limit 14 output overvoltage and undervoltage protection 14 led open detect 15 undervoltage protection (uvp) 15 led short detect 16 input uvlo 16 vdd and vdr 16 shutdown 17 fault protection during operation 17 application information 19 paralleling more than one A8508 19 design example 21 typical applications 24 package outline drawing 27
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional block diagram vdd vdr regulator uvlo internal soft start enable pwm thermal shutdown open/short led detect iset pad fault led driver 1.25 v ref driver circuit internal v dd v ref1 v ref v ref2 v ref i ss i ss agnd current sense fb fault ovp/uvp sense oscillator gate vin fset/sync comp mode pwm en pgnd et and lp packages only agnd iset ovp led2 led1 led4 led5 led6 led7 led8 led3 fault agnd fb + ? + ? + ? + ? 100 k senp senn 100 k 70 k 50 a
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin-out diagrams terminal list table name number function et lp, lw agnd 13 19 led ground. comp 23 5 output of the error amplifier and compensation node. connect a compensation network from this pin to ground. en 25 7 enable for the A8508. f a u l t 312 this pin is used to indicate a fault condition. connect a pull-up resistor between this pin and the required logic level voltage. the pin is an open drain type configuration that will be pulled low when a fault occurs. fset/sync 27 9 frequency/synchronization pin. a resistor rfset from this pin to ground sets the switching frequency. this pin can also be used to synchronize two or more converters in the system. gate 21 3 gate pin for driving external n-channel fet. hvgate 5 n.a. input disconnect switch: gate driver iset 28 10 connect the riset resistor between this pin and ground to set the 100% led current. led1 17 23 connect the cathode of each led string to these pins. led2 16 22 led3 15 21 led4 14 20 led5 10 18 led6 8 17 led7 11 16 led8 12 15 mode 24 6 this pin is used to determine the mode of operation. mode high tied to vdd allows parallel operation, and mode low is used for single ic operation. ovp 4 13 this pin is used to sense an overvoltage (ovp) condition. connect the rovp resistor from vout to this pin to adjust the overvoltage protection. pad ? ? for qfn and tssop packages, this exposed pad provides enhanced thermal dissipation. this pad must be connected to the ground plane(s) of the pcb with at least 8 vias, directly in the pad solder pad. pgnd 18 24 power ground for the internal gate driver circuit. pwm 26 8 pwm dimming pin. used to control the led intensity by using pulse width modulation. the typical pwm dimming frequency is in the range of 100 to 1000 hz. senn 19 1 negative sense line for boost switch current sensing. senp 20 2 positive sense line for boost switch current sensing. vdd 1 11 output of internal ldo regulator. connect a 0.1 f decoupling capacitor between this pin and ground. vdr 22 4 output of the gate driver bias voltage regulator. connect a 0.22 f capacitor in series with a 7.5 resistor between this pin and ground. vin 7 14 input power to the A8508. vsense 6 n.a. input disconnect switch: current sense 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 pgnd led1 led2 led3 led4 agnd led5 led6 led7 led8 vin ovp senn senp gate vdr comp mode en pwm fset/sync iset vdd fault 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 pgnd led1 led2 led3 led4 agnd led5 led6 led7 led8 vin ovp senn senp gate vdr comp mode en pwm fset/sync iset vdd fault pad lp package et package lw package pad 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 iset fset/sync pwm en mode comp vdr led6 nc led5 led7 led8 agnd led4 gate senp senn pgnd led1 led2 led3 vdd nc fault ovp hvgate vsense vin
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1 valid at v in = 12 v, t a = 25c, indicates specifications guaranteed by design and characterization over the full operating temperature range with t a = t j = ?40c to 105c; unless otherwise noted characteristics symbol test conditions min. typ. max. unit input voltage specifications operating input voltage range v in 9 ? 40 v uvlo start threshold v uvlo(th) v in rising ? ? 8.5 v uvlo hysteresis v uvlo(hys) v in falling ? 400 ? mv input currents input quiescent current i q en = v ih ; f sw = 800 khz, no load ? 7 ? ma input sleep supply current i qsleep v in = 12 v, en = fset/sync = 0 v ? 0.5 10.0 a input logic levels (en, pwm, mode, fset/sync) input logic level-low v il 9 v < v in < 40 v ? ? 400 mv input logic level-high v ih 9 v < v in < 40 v 1.5 ? ? v en and pwm pins pull-down resistor r pulldown en, pwm= 5 v ? 100 ? k mode pin pull-down resistor r mode mode=2.5 v ? 70 ? k error amplifier open loop voltage gain a vol ? 47 ? db transconductance g m i comp = 10 a ? 990 ? a/v source current i ea(src) v comp = 1.5 v ? ?360 ? a sink current mode high i ea(sink)h v comp = 1.5 v, mode = v ih ? 80 ? a sink current mode low i ea(sink)l v comp = 1.5 v, mode = v il ? 360 ? a comp pin pull-down resistor r comp f a u l t = 0 ? 1.5 ? k soft start comp level v compss ? 200 ? mv overvoltage protection overvoltage threshold v ovp(th) ovp connected to vout 1.11 1.25 1.4 v ovp sense current i ovph 45 49 53 a output undervoltage threshold v uvp(low) falling ? 100 ? mv v uvp(high) rising ? 120 ? mv boost switch gate driver gate driver voltage v drv measured at gate pin ? 7 ? v driver pull-up and pull-down resistance r gateud measured at v gate =v drv / 2 ? 4.5 ? driver to ground resistance r gateg en = 0, vin = 0 ? 200 ? k sense positive v sensep 85 100 115 mv secondary sense positive v sensesec ? 165 ? mv continued on the next page?
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com boost switch gate driver (continued) soft start boost current limit reference voltage v swss(lim) reference voltage for boost switch current limit during soft start. ? 39 ? mv minimum switch on-time t swontime ?? 110 ns minimum switch off-time t swofftime ?? 85 ns oscillator frequency oscillator frequency f sw r fset = 7.5 k 725 800 875 khz r fset = 10 k 540 600 660 khz r fset = 20 k ? 300 ? khz fset/sync pin voltage v fset r fset = 8.25 k ? 1.00 ? v synchronization synchronized pwm frequency f swsync 300 ? 800 khz synchronization input minimum off-time t pwsyncoff 150 ?? ns synchronization input minimum on-time t pwsyncon 150 ?? ns led current sinks ledx accuracy err led i set = 100 a ? 0.7 ? % ledx matching ledx i set = 100 a ? 0.8 2.5 % ledx regulation voltage v led v led1 through v led8 all equal, i set = 100 a ? 650 ? mv i set to i ledx current gain a iset i set = 100 a ? 1160 ? a/a iset pin voltage v iset ? 1.000 ? v allowable iset current i set 34 ? 130 a ledx pin short detect v ledsc while led sinks are in regulation, sensed from ledx pin to gnd 4.6 ?? v soft start ledx current gain i ledss current through each enabled ledx pin during soft start, r iset = 12.4 k ? 44 ? a/a pwm high to led-on delay t dpwm(on) time between pwm enable and ledx current reaching 90% of maximum ? 0.5 1.1 s pwm low to led-off delay t dpwm(off) time between pwm enable going low and ledx current reaching 10% of maximum ?? 500 ns electrical characteristics 1 (continued) valid at v in = 12 v, t a = 25c, indicates specifications guaranteed by design and characterization over the full operating temperature range with t a = t j = ?40c to 105c; unless otherwise noted characteristics symbol test conditions min. typ. max. unit continued on the next page?
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics 1 (continued) valid at v in = 12 v, t a = 25c, indicates specifications guaranteed by design and characterization over the full operating temperature range with t a = t j = ?40c to 105c; unless otherwise noted characteristics symbol test conditions min. typ. max. unit f a u l t pin f a u l t pin pull-down voltage v fault i fault = 1 ma (400 internal switch resistance) ? 0.4 ? v f a u l t pin leakage current i faultlkg v fault = 5 v ?? 1 a thermal protection (tsd) thermal shutdown threshold 2 t sd temperature rising ? 165 ? oc thermal shutdown hysteresis 2 t sdhys ? 20 ? oc 1 for input and output current specifications, negative current is defined as coming out of the node or pin (sourcing), positive current is defined as going into the node or pin (sinking). 2 ensured by design and characterization, not production tested. 643 644 645 646 647 648 649 650 651 652 653 654 -40-20 0 20406080100 ledx regulation voltage, v regx (mv) junction temperature, t j (c)
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description enabling the ic the ic turns on when a logic high signal is applied on the en pin, and the input voltage present on the vin pin is greater than the 8.5 v necessary to clear the uvlo (v uvlorise ) threshold. before the leds are enabled, the A8508 driver goes through a system check to determine if there are any possible fault condi- tions that might prevent the system from functioning correctly. powering up: led pin short-to-gnd check after the vin pin goes above the uvlo threshold, and a high sig- nal is present on the en pin, the ic proceeds to check if any ledx pins are shorted to gnd and/or are not used. each unused pin should be connected to gnd with a 4.75 k pull-down resistor. after the voltage threshold on the ledx pins exceeds 120 mv, a timer of 1536 clock cycles (2 ms at 800 khz switching frequency, see figure 2) is applied during which the A8508 determines the status of the pins. any unused pin connected to gnd with the pull-down resistor will be taken out of regulation at this point and will not contribute to the boost regulation loop (see figure 3). a typical example is shown in figure 4. when a pin is connected to gnd through a 4.75 k resistor, the voltage on that ledx pin during the led detection period is about 200 mv. this is shown in figure 2. if an ledx pin is shorted to ground such that ledx pin voltage is < 100 mv, the A8508 will not proceed with soft start until the short is removed from the ledx pin. this prevents the A8508 figure 4. channel select setup: (left) channel led8 not used, (right) using all channels. gnd 4.75 k A8508 led1 led2 led3 led4 led5 led6 led7 led8 A8508 led1 led2 led3 led4 led5 led6 led7 led8 gnd figure 3. led detect circuit operation for an led pin that is not being used; shows v out (ch1, 10 v/div.), v en (ch2, 5 v/div.), an unused ledx with a 4.75 k resistor from this pin to gnd, v leda (ch3, 500 mv/div.), and a used ledx, v ledb (ch4, 500 mv/div.), t = 2 ms/div. figure 2. led detect circuit operation for two connected leds at f sw = 800 khz; shows v out (ch1, 10 v/div.), v en (ch2, 5 v/div.), an ledx, v leda (ch3, 500 mv/div.), another ledx, v ledb (ch4, 500 mv/div.), t = 2 ms/div. t v leda (not used) v ledb (used) v out v en c1 c3 c4 c2 figure 5. led detect circuit operation: device powers-up after the short is removed from the led pin; shows v out (ch1, 10 v/div.), v en (ch2, 5 v/ div.), an ledx with short, v leda (ch3, 500 mv/div.), and an ledx without short, v ledb (ch4, 500 mv/div.), t = 2 ms/div. t led detection period short removed v en v out v leda (with temporary short) v ledb (no short) c1 c3 c4 c2 t led detection period v en v leda v ledb v out c1 c2 c3 c4
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com from powering-up and putting an uncontrolled amount of current through the leds. after the short is removed the affected ledx pin will rise up to the 500 mv level. when the ledx pin voltage exceeds the 260 mv threshold, the ic detects connected leds and proceeds with led detection and soft start. figure 2 shows a case when two led channels are enabled. during the led detection period, voltage on both ledx pins > 260 mv. figure 5 shows a case with leda temporarily shorted to ground and ledb in normal operation. soft start function during soft start the led current gain is reduced to (i ledss ). as an example, for a 120 ma output current, the soft-start led current would be set to about 4.5 ma (see figure 7). also dur- ing soft start the boost switch sense voltage is reduced to the i swss(lim) level, to limit the initial inrush current generated by the charging of the output capacitors. the actual current limit (i lim ) is equal to: i lim = v swss(lim) / r sense (1) where v swss(lim) is found in the electrical characteristics table, and r sense is the current sense resistor value. when the converter senses that there is enough voltage on the ledx pins, the converter proceeds to increase the led current to the preset regulation current and the boost switch current sense voltage limit is switched to the i sw(lim) level to allow the A8508 to deliver the necessary output power to the leds (figure 8). figure 8. normal start-up behavior; shows ven (ch1, 2 v/div.), v comp (ch2, 2 v/div.), i in (ch3, 1 v/div.), and v out (ch4, 10 v/div.), t = 500 s/div. figure 6. start-up operation, individual ledx current = 60 ma, boost sense resistor = 0.020 ; shows v en (ch1, 2 v/div.), i in (ch2, 1 a/div.), i out (ch3, 200 ma/div.), and v out (ch4, 20 v/div.), t = 500 s/div. figure 7. start-up operation, individual ledx current = 120 ma, boost sense resistor = 0.010 ; shows v en (ch1, 2 v/div.), i in (ch2, 2 a/div.), i out (ch3, 1 a/div.), and v out (ch4, 20 v/div.), t = 500 s/div. t i in limited by boost switch to v swss(lim) / r sense v en i in v out i out c1 c3 c4 c2 t c1 c3 c4 c2 i in limited by boost switch to v swss(lim) / r sense v en i in v out i out t boost starts operating in normal current limit v sw(lim) c1 c3 c4 c2 i in limited by boost switch to v swss(lim) / r sense v out sufficient to begin normal power-up v en v comp v out i in
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com frequency selection the switching frequency on the boost regulator is set by connect- ing a resistor, rfset, between the fset/sync pin and ground. the switching frequency range is 300 to 800 khz, with example values of: r fset value (k ) swtiching frequency, f sw (khz) 7.5 800 10 600 the relationship of r fset and f sw is shown in figure 9. the fset/sync pin has short-to-ground protection. if the fset/sync pin is held low for more than 4 s typical, the A8508 will stop switching and disable the ledx pins (see figures 10 and 11). if the fset/sync pin is released at any time after 7 s, the A8508 will proceed to soft start but will not perform the led detection phase. synchronization the A8508 can also be synchronized by using an external clock connected to the fset/sync pin. the synchronization func- tion of ic was designed to work with a push-pull type of clock driver. the amplitude of the clock signal should be between 1.5 and 3.3 v. the synchronization clock should have duty cycles that meet the minimum on/off times. figure 12 shows the timing for a synchronization clock into the A8508 at 800 khz. the 150 ns minimum on-time and 150 ns minimum off-time are figure 10. shutdown when the fset/sync pin is shorted to ground; shows v out (ch1, 10 v/div.), v fset/sync (ch2, 1 v/div.), i in (ch3, 2 a/div.), and i out (ch4, 500 ma/div.), t = 200 s/div. figure 11. zoomed-in view of figure 9, showing quick shutdown when fset/sync shorted to ground, preventing ic running at very high frequency; shows v out (ch1, 10 v/div.), v fset/sync (ch2, 1 v/div.), i in (ch3, 2 a/div.), and i out (ch4, 1 a/div.), t = 10 s/div. 150 ns t = 1.25 s 950 ns t pwsyncon t pwsyncoff 150 ns 200 300 400 500 600 700 800 900 7 9 11 13 15 17 19 21 fset resistor value, r fset (k ) switching frequency, f sw (khz) figure 12. sync pulse minimum on and off time requirements, for an 800-khz clock. figure 9. switching frequency as determined by r fset value. t fset/sync shorted to gnd v out v fset/sync i in i out c1 c3 c4 c2 t fset/sync shorted to gnd v out v fset/sync i in i out c1 c3 c4 c2
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com indicated by the specifications for t pwsyncon and t pwsyncoff . thus any pulse with a duty cycle of 19% to 85% at 800 khz will synchronize the ic. it is recommended to also use the rfset resistor with the external clock signal. if a synchronization clock is lost during operation, the ic will revert to the preset switching frequency that is set by the rfset resistor. in this configuration the preset frequency does not have any restrictions other than the normal operating range of 300 to 800 khz. during the changeover period the ic stops switching for an approximately 5 s period to allow the synchronization detection circuitry to switch over to the exter- nal preset switching frequency. although examples shown in figures 13 and 14 are extreme cases of clock-to-resistor frequency changes, it is recommended that actual applications not have such large switching frequency changes. in most applications the rfset resistor and clock fre- quency should be very close to each other in terms of frequency. setting the frequencies close together will prevent the system from experiencing large changes on frequency-dependent signals and components, such as the inductor ripple current and the com- pensation resistor and capacitor. led current setting and led dimming the maximum led current can be up to 150 ma per channel. the led current is set through the riset resistor connected between the iset pin and ground. the i led current is set accord- ing to the following formula: r iset = (1.000 / i led ) 1160 (2) where r iset is in , and i led is in a. this sets the maximum cur- rent through the leds, referred to as the 100% current . standard r iset values are as follows: standard resistor value closest to r iset (k ) led current per led, i led (ma) 7.87 150 9.53 120 11.5 100 14.3 80 19.1 60 figure 13. synchronization feature with 200 khz difference between r fset and external clock signal. the synchronization frequency is 600 khz, and the resistor preset frequency is 800 khz. note that there is very little disturbance in the led current at the time of changeover; shows v gate (ch1, 5 v/div.), v comp (ch2, 1 v/div.), i out (ch3, 1 a/div.), and v fset/sync (ch4, 5 v/div.), t = 5 s/div. figure 14. synchronization feature with 500 khz difference between r fset and external clock signal, illustrating the flexibility of the rfset/sync pin; synchronization frequency is 300 khz, and the resistor preset frequency is 800 khz; shows v gate (ch1, 5 v/div.), v comp (ch2, 1 v/div.), i out (ch3, 1 a/div.), and v fset/sync (ch4, 5 v/div.), t = 10 s/div. t changeover period f sw = 600 khz from sync pulse f sw = 800 khz from rfset value v fset/sync i out v gate v comp c1 c3 c4 c2 t changeover period f sw = 300 hz from sync pulse f sw = 800 hz from rfset value v fset/sync i out v gate v comp c1 c3 c4 c2
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com t v out i out v comp v pwm c1 c3 c4 c2 the cited values are for 1% tolerance resistors. if the calculated value was not present, the next lowest value of 1% resistor was chosen. pwm dimming applying an external pwm signal on the pwm pin performs pwm dimming. when the pwm pin is pulled high, the A8508 enables the ledx pins to sink 100% current. when pwm is pulled low, the boost converter and ledx sinks are turned off. the compensation (comp) pin is floated, and critical internal circuits are kept active. the typical pwm dimming frequencies fall between 100 and 1000 hz. figures 15 and 16 show examples of dimming at 50% and 0.5% duty cycles. analog dimming the A8508 can also be dimmed by using an external dac or other voltage source applied either directly to the ground side of the riset resistor or through an external resistor to the iset pin (see figure 17). the iset current can be varied in the range between 34 a and 130 a. ? for a single-resistor configuration (panel a of figure 17), the iset current is controlled by the following formula: i set = v iset ? v dac r iset (3) where v iset is the iset pin voltage and v dac is the dac output voltage. ? for a dual-resistor configuration (panel b of figure 17), the iset current is controlled by the following formula: i set = ? v iset r iset v dac ? v iset r 1 (4) the advantage of this circuit is that the dac voltage can be higher or lower, thus adjusting the led current to a higher or lower value of the preset led current set by the r iset resistor: ? v dac = 1.00 v: output is strictly controlled by r iset ? v dac > 1.00 v: led current is reduced ? v dac < 1.00 v: led current is increased figure 15. pwm dimming: f sw = 200 hz, 50% duty cycle, v out = 30 v, v in = 12 v, and i led = 120 ma per led string; shows v out (ch1, 10 v/div.), i out (ch2, 500 ma/div.), v comp (ch3, 2 v/div.), and pwm (ch4, 5 v/div.), t = 2 ms/div. figure 16. pwm dimming: f sw = 200 hz, 0.5% duty cycle, v out = 30 v, v in = 15 v, i led = 120 ma per led string; shows v out (ch1, 10 v/div.), i out (ch2, 500 ma/div.), v comp (ch3, 2 v/div.), and v pwm (ch4, 5 v/div.), t = 10 s/div. figure 17. typical application simplified diagram of voltage led current control using a dac to control led current. t c1 c3 c4 c2 v out i out v comp v pwm gnd dac vdac gnd A8508 iset gnd dac vdac gnd A8508 iset r iset r1 r iset a b
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com boost switch overcurrent protection the boost switch is protected with pulse-by-pulse current limiting set by the external rsense resistor. there also is a secondary current limit that is sensed on the boost switch. setting the current sense resistor the current sense resistor (see figure 18) is set according to the following formula: i lim = v senp r sense (5) where v senp is found in the electrical characteristics table, and r sense is the current sense resistor value. the current limit is calculated by the following formula: i lim = i in (max) + ? i l 2 (6) where i in (max) is the maximum input current, and i l is the inductor current ripple. current sense resistor routing the current sense resistor must be routed as a differential pair to minimize measurement accuracy errors. for most current sense resistors the resistance is measured between the inside edges of the mounting pads of the rsense resistor. figure 19 shows correct differential current sensing connections to the A8508. the individual current sense traces are kept short and side-by-side to get proper signal voltage levels. the trace for the positive sense pin (senp) must be routed to the inside edge of the mounting pad on the high side of rsense. the trace for the negative sense pin (senn) must be routed to the inside edge of the mounting pad on the ground side of rsense. it should be noted that when designing the pcb layout, the trace for the negative sense pin (senn) is often automatically merged with the ground flood fill and with the mounting pad on the ground side of rsense (shown in figure 20). however, the trace must be kept separate and dedicated, and careful attention must be given when routing the pcb. figure 18. simplified schematic of the current sense resistor connections to the current sense amplifier. figure 19. correct layout of current sense resistor traces: (a) connect to inside edges of pads, (b) parallel and dedicated figure 20. incorrect layout of current sense resistor traces: (a) do not connect to outside edge of pad, (b) do not merge trace into ground A8508lp gnd senp senn rsense a a b A8508lp gnd senp senn rsense a b current sense + ? senp A8508 senn rsense
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 14 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com t v out v comp v gate i l c1 c3 c4 c2 pulse-by-pulse current limit figure 21 illustrates the normal waveform for the current sense signal. the pulse-by-pulse current limit is designed to limit the current through the external mosfet to prevent failure. when the v sensep threshold is reached, the ic stops switching to allow the inductor current to fall. operation of pulse-by-pulse current limiting is shown in figure 22. A8508 vout ovp rovp a b figure 21. current sense signal (v sense ) during normal operation, showing large spikes that are filtered out by a blanking period to avoid false overcurrent tripping; r sense = 10 m ; shows inductor current i l (ch1, 1 a/div.), v sense (ch2, 20 mv/div.), and gate voltage of the main boost switch v gate (ch3), t = 500 ns/div. figure 22. typical pulse-by-pulse current limit; shows i l (ch1, 2 a/div.), v out (ch2, 10 v/div.), v comp (ch3, 2 v/div.), and v gate (ch4), t = 500 ns/div. figure 23. simplified schematic of the overvoltage protection section. figure 24. ovp resistor connections; (a) connection should be short, (b) connection to vout can be long, and rovp should be as close to the ovp pin as possible. ovp 1.25 v 50 a 100 mv + ? + ? uvp A8508 ovp vout rovp t normal spikes due to switching v gate v sense i l c1 c3 c2 secondary boost switch limit in case there is an inductor short during operation ,the A8508 has a secondary switch current limit. when this threshold is reached, the ic immediately shuts down. the level of this current limit is set above the pulse-by-pulse current limit to protect the switch from destructive currents when the boost inductor is shorted. output overvoltage and undervoltage protection the ovp pin on the A8508 controls both the overvoltage (ovp) and undervoltage (uvp) protection features. the pin circuit is shown in figure 23. the ovp protection protects the boost con- verter from excessive voltage levels when the feedback control loop is broken, usually caused by an open connection from output voltage to the leds. the uvp function provides output voltage- to-ground short protection when an external disconnect switch is used. for more detailed information on disconnect switch appli- cation, see the undervoltage protection (uvp) section. for proper operation of this pin, due to the relatively low voltage level, special care has to be taken during pcb layout. figure 24 is an example of a proper pcb layout.
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 15 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com led open detect when any led string opens, the boost control circuit increases the output voltage until it reaches the overvoltage protection level. the ovp event causes any led string that is below regula- tion level to be disabled. after disabling the open string, the output voltage returns to normal operating voltage. an en low signal will reset the led string regulation lock. figure 25 shows a typical overvoltage condition when the output voltage is disconnected from the led load. figure 26 shows an extended view of the same situation. figure 27 shows an ovp condition created by a single open led string. undervoltage protection (uvp) if the output voltage is shorted to ground the ovp pin will sense an undervoltage condition (uvp). when uvp is sensed, the ic sets the fault ag low which, if used to interface to the output- disconnect switch, will shut off the p-fet device. figure 28 is a schematic showing the input disconnect switch implementation. figure 25. ovp operation with all ledx pins open. v out rises to the overvoltage level and stays there until the ic is shut down; shows v out (ch1, 20 v/div.), i out (ch2, 1 a/div.), and v comp (ch3, 2 v/div.), t = 2 ms/div. figure 26. extended view of the ovp condition in figure 25; shows v out (ch1, 20 v/div.), i out (ch2, 1 a/div.), v comp (ch3, 1 v/div.), and switch node (v sw ) (ch4, 20 v/div.), t = 10 ms/div. figure 27. ovp condition created by an open led string; shows v out (ch1, 2 v/div.), pin voltage v ledx (ch2, 5 v/div.), and i out (ch3, 200 ma/div.), t = 2 ms/div. t v comp begins to decrease ovp level fault occurrence v out i out v comp c1 c3 c2 t periodic switch node bursts occur when all ledx pins are open v out i out v comp v sw ovp level c1 c3 c4 c2 t led string opens ovp limit is reached, and string is removed from control loop control loop reduces v out to new regulation level v out (30 v) v ledx i out c3 c2 figure 28. simplified schematic of an external disconnect switch implementation. v dr v in A8508 c in (optional) ao4421 2n7002 10 k 1 k 1 k l1 fault
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 16 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 29. input disconnect switch shutdown during an output short condition; shows v out (ch1, 20 v/div.), i in (ch2, 10 a/div.), f a u l t (ch3, 5 v/div.), and pmos device v gate (ch4, 5 v/div.), t = 50 s/div. figure 30. typical shorted led: when voltage exceeds v ledsc , the led is disabled and remains disabled until either the en pin is toggled or the power cycled; shows v out (ch1, 20 v/div.), v en (ch2, 5 v/div.), i out (ch3, 0.5 a/div.), and v ledx (ch4, 10 v/div.), t = 10 s/div. the waveforms in figure 29 show the operation of the disconnect feature. led short detect all ledx pins are rated for 55 v, thus allowing ledx pin-to- vout short protection in case of a connector short. any ledx pin that has a voltage exceeding v ledsc will be removed from operation. this is to prevent the ic dissipating too much power by having a large voltage present on the ledx pins. input uvlo when v in rises above the uvlo threshold (v uvlo(th) ), the A8508 is enabled. it is disabled when v in falls below v uvlo(th) ? v uvlo(hys) for more than 2 s. this lag is to avoid shutdown because of momentary glitches in the power supply. vdd and vdr the vdd pin provides the regulated bias supply for the internal circuits. a capacitor with a value in the range 0.1 to 1 f should be used to decouple the internal analog and digital circuitry. t v out i in i in v gate(pmos) output short occurrence c1 c3 c4 c2 fault t v ledsc is detected v out v en i out v ledx c1 c3 c4 c2
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 17 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the vdr circuit provides power to the gate driver of the A8508. for best stability, use a decoupling capacitor in series with a resistor between the vdr pin and gnd. the recommended value for the decoupling capacitor is 0.22 f. the value of the series resistor is typically between 5 and 10 . if necessary, a larger resistor value may be used to limit the rising slope of the gate signal, in order to reduce emi. shutdown if the en pin is pulled low, the ic will shut down immediately. fault protection during operation the A8508 device constantly monitors the state of the system to determine if any fault conditions occur during normal opera- tion. the response to a triggered fault condition is summarized in table 1. the possible fault conditions that the part can detect are: ? open led pin ? shorted inductor with second level switch current protection ? vout short-to-ground ? iset pin short-to-ground ? fset pin short-to-ground ? shorted led ? open schottky diode ? short schottky diode protection with second level switch cur- rent protection ? thermal shutdown (tsd) ? overvoltage protection (ovp) figure 31. input disconnect switch power-up: (1) v out charges via 10 k resistor, (2) i in current spike from charging cout when the pmos is enabled; shows v out (ch1, 20 v/div.), i in (ch2, 2 a/div.), f a u l t (ch3, 5 v/div.), and pmos device v gate (ch4, 5 v/div.), t = 2 ms/div. t led detection period soft start and power-up v gate(pmos) v out i in c1 c3 c4 c2 1 2 fault
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 18 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table 1. fault modes fault name type active fault flag set description boost sink driver primary switch current protection (pulse-by- pulse current limit) auto-restart always no this fault condition is triggered by the pulse-by-pulse current limit when the sensp pin voltage exceeds v sensep . off for a single cycle on secondary switch current limit latched always yes when the current through the boost switch exceeds the secondary current limit (v sensesec ) the ic immediately shuts down the led drivers and the boost. to re-enable the A8508 the en pin must be toggled. off off ledx pin short to gnd protection auto-restart startup yes this fault prevents the ic from starting-up if any of the ledx pins are shorted. the ic stops soft start from starting while any of the ledx pins are determined to be shorted. after the short is removed, soft start is allowed to start. off off ledx pin open auto-restart normal operation no when an ledx pin is open the device will determine which ledx pin is open by increasing the output voltage until ovp is reached. any led string below regulation will be turned off. the device then goes back to normal operation by reducing the output voltage to the appropriate voltage level. on off for open pins. on for all others led short protection auto-restart always no this fault occurs when the led pin voltage exceeds v ledsc . when the led short protection is detected, the led string that is above the threshold will be removed from operation. on off for shorted pins. on for all others fset pin short protection auto-restart always no this fault occurs when the fset pin current goes above 150% of the maximum current. the boost stops switching, and the ic disables the led sinks until the fault is removed. when the fault is removed the ic tries to restart with soft start. off on in soft start current iset pin short protection auto-restart always no this fault occurs when the iset pin current goes above 150% of the maximum current. the boost stops switching and the ic disables the led sinks until the fault is removed. when the fault is removed the ic tries to regulate to the preset led current. off off overvoltage protection auto-restart always no the fault occurs when the ovp pin voltage exceeds the v ovp(th) threshold. the A8508 immediately stops switching to try to reduce the output voltage. if the output voltage decreases then the A8508 restarts switching to regulate the output voltage. stop during ovp event on output undervoltage protection auto-restart always yes this fault occurs when the ovp pin senses less than 100 mv on the pin. the ic disables the external p-fet switch, if one is used. off off overtemperature protection auto-restart always yes the fault occurs when the die temperature exceeds the overtemperature threshold, typically 165c. off off vin uvlo auto-restart always no this fault occurs when v in drops below v uvlo(th) (max), 8.5 v. this fault resets all latched faults. off off
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 19 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com application information paralleling more than one A8508 the A8508 can be paralleled together by using a single boost converter (master) to provide output power for up to a total of four A8508s (slaves). the mode pin of each device must be tied to the vdd pin of the same device for proper mode selection. in this mode, the f a u l t pins and the comp pins become a bi- direction signal bus for the system to communicate. at initial power-up, each ic will release a pull-down resistor on the comp pin and start in soft start mode. when 200 mv is detected on the comp pin, the master will then switch to normal mode. also, for proper operation all of the f a u l t pins must be tied together to prevent the parallel ics from powering-up into a shorted ledx pin situation. while the f a u l t pins are pulled low, the system will not proceed with start-up. below is a simple list of necessary connections between the master and slave(s), to ensure proper parallel operation (refer to application c in the typical applications section): ? comp pin ? vout node ? f a u l t pin ? en pin ? pwm pin each one of these must be connected to the corresponding signal on the slave devices. ovp setting for parallel operation a notable exception to the list is the ovp pin. in this system each ovp pin must be set with a dedicated resistor. to make sure that the system will operate properly, the overvoltage protection on the master ic should be set higher than on the slave ic. the A8508 checks open led condition upon hitting the ovp voltage. if the master ovp voltage is set lower than the slave ovp, the slave ovp pin will not trip to permit the open led check. this in turn will not remove the corresponding ledx pins from regula- tion. therefore, the output voltage will stay at the master ovp limit and never decrease the output voltage to the lower regula- tion level. the required slave ovp resistor value can be calculated using the following formula: r ovp(slave) = v out(ovp) ? 1.25 v i ovph (min) (7) where v out(ovp) is the required ovp voltage level, and i ovph (min) is the current into the ovp pin found in the electrical characteristics table. the minimum value should be used in this calculation. the required master ovp voltage level can be calculated using the following formula: v ovp(master) = r ovp(slave) i ovph (max) + 1.25 (8) where v ovp(master) is the minimum ovp voltage level of the master ic, i ovph (max) is current into the ovp pin found in the electrical characteristics table. the maximum value should be used in this calculation. the required master ovp resistor value can be calculated using the following formula: r ovp(master) = v ovp(master) ? 1.25 v i ovph (min) (9) where v ovp(master) is the minimum required master ovp voltage level, and i ovph (min) is the current into the ovp pin found in the electrical characteristics table. the minimum value should be used in this calculation. following the above formulas will guarantee that there is no overlap in ovp voltage levels in the system. all slave A8508s in the system can have the same ovp voltage setting. figure 32 shows a proper master-slave ovp setting, and figure 33 shows the result of setting the master ovp too low.
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 20 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com figure 33. ovp on the master ic is set too low and the ic does not respond properly to the open led condition on the slave ic; shows v out (ch1, 10 v/div.), v ledx (ch2, 2 v/div.), and i out (ch3, 200 ma/div.), t = 100 ms/div. figure 32. proper ovp setting for the master and slave configuration. the master ovp is set higher than the slave, shows v out (ch1, 2 v/div.), pin voltage v ledx (ch2, 2 v/div.), and i out (ch3, 200 ma/div.), t = 2 ms/div. t led string opens ovp limit is reached, and string is removed from control loop control loop reduces v out to new regulation level v out (30 v) v ledx i out c3 c2 t ovp of slave is never exceeded, so v out remains higher than necessary system v out clamped to ovp setting of master ic v out v ledx i out c1 c3 c2 led string opens
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 21 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com design example this section provides a method for selecting component values when designing an application using the A8508. assumptions: for the purposes of this example, the following are given as the application requirements: ? v in : 10 to 16 v ? quantity of led channels, #channels: 8 ? quantity of series leds per channel, #seriesleds : 10 ? led current per channel, i led : 120 ma ? v f(120) at 120 ma: 3.2 v (max) ? f sw : 600 khz ? t a (max): 65c ? pwm dimming frequency: 200 hz, 1% duty cycle step 1: connect leds to pins led1 through led8. step 2: determine the led current by setting resistor r iset . to do so, apply equation 2: r iset = (1.000 / i led ) 1160 = (1.000 v / 0.120 a ) 1160 = 9.67 k choose a 9.53 k resistor. step 3: determine the ovp resistor. the ovp resistor is con- nected between the ovp pin and the output voltage of the con- verter. the first step is to determine the maximum voltage based on the led requirements. then the regulation voltage of 600 mv should be added, along with 2 v for noise and regulation. given the regulation voltage (v led ) of the A8508 is 850 mv, the mini- mum required voltage can be determined as follows: v out(ovp) v out(ovp)(min) = #seriesleds v f(120) + v led + 2 v = 10 3.2 v + 0.650 v + 2 v = 34.65 v (10) the ovp resistor (rovp) value can be calculated as: r ovp = v out(ovp)(min) ? v ovp(th) (min) i ovph (min) = 34.65 v ? 1.11 v 745 k ; use the nearest standard value, 750 k 45 a = (11) where both i ovp(th) (min) and v ovp(th) (min) are found in the electrical characteristics table. choose a value of resistor that is the closest value higher than the calculated r ovp . in this design example, a value of 750 k is selected. below is the actual value of the minimum ovp trip level with the selected resistor, applying equation 8: v ovp = r ovp i ovph + 1.25 v = 750 k 49 a + 1.25 v = 38.75 v step 4: determine the inductor. the inductor must be chosen such that it can handle the necessary input current. in most appli- cations, due to stringent emi requirements, the inductor must operate in continuous conduction mode throughout the whole input voltage range. step 4a: determine the maximum duty cycle of the system: d (max) = = v in (min) = 74.5% 1 ? 1 ? v out(ovp) + v f(boost) 10 v 0.9 34.65 v + 0.4 v (12) a good approximation of efficiency ( ) is 90%. the voltage drop of the boost diode can be approximated to be about 0.4 v. step 4b: determine the maximum and minimum input current to the system. the minimum input current dictates the inductor value. the maximum current rating dictates the current rating of the inductor. to calculate the maximum input current, first determine the required output current: i out = #channels i led 8 120 ma = = 0.960 a (13) then substitute into the formula for maximum input current: i in (max) = = v in (min) = 3.7 a v out i out 34.65 v 0.960 a 10 v 0.90 (14)
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 22 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the minimum input current can be calculated as: i in (min) = = v in (max) = 2.31 a v out i out 34.65 v 0.960 a 16 v 0.90 (15) step 4c: determining the inductor value. to assure that the inductor operates in continuous conduction mode, the value of inductor must be set such that 1 / 2 of the inductor ripple current is not greater than the average minimum input current. as a first pass, take i ripple to be 30% of the maximum inductor current: ? i l = i in (max) ( i ripple / i in (max)) 3.72 a 0.30 = = 1.1 a (16) check to make sure that 1 / 2 of the inductor ripple current is less than i in (min): ? i l > > 2.31 a 0.56 a 1 2 i in (min) the inductor value can be calculated as: l = = ? i l f sw v in (min) = 10.62 h d (max) 0.745 10 v 1.1 a 600 khz (17) a good inductor value to use would be l used = 10 h. step 4d: determining the inductor current rating. the inductor current rating must be greater than the i in (max) value plus the ripple current i l , calculated as: i l (min) i in (max) + = = 4.28 a = 3.72 a + 0.56 a ? i lused 1 2 (18) step 4e: choosing the rsense resistor. the sense resistor value can be calculated as follows: r sense = 0.086 v 4.28 a v sensep i l (min) 0.02 = = (19) 0.018 is a good value to use for the resistor. step 4f: this step is used to verify that there is sufficient slope compensation for the inductor chosen. the internal slope com- pensation value is determined by the following formula: = 2.8110 ?7 f sw = 0.168 v / s slope compensation where f sw is in hz. substituting: (20) with r sense = 0.02 this translates to: 0.168 / 0.02 = 8.4 a/ s next invert equation 17 and insert the inductor value used in the design: ? i lused = = l used f sw where f sw is in mhz. substituting: v in (min) = 1.24 a d (max) 0.745 10 v 10 h 600 khz (21) ? i lused 1 10 ?6 = = f sw = 2.91 a / s 1 inductor current slope (1 ? d (max)) (1 ? 0.745) 1.24 a 1 10 ?6 1 600 khz (22) note: that the 110 ?6 is a constant multiplier. this slope should be smaller than the internal slope compensation. step 5: to determine the resistor values for a switching fre- quency use figure 9. step 6: choosing the proper switching diode. the switching diode must be chosen for three characteristics when it is used in led lighting circuitry: reverse voltage rating, current rating, and reverse current characteristic of the diode.
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 23 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the reverse voltage rating should be such that, during any opera- tion condition, the voltage rating of the device is larger than the maximum output voltage. in this case, the maximum output volt- age is v out(ovp) . the peak current through the diode is: i d(peak) = = ? i lused i in (max) + = 0.56 a 3.72 a + 4.28 a (23) the other major component in determining the switching diode is the reverse current characteristic of the diode. this characteristic is especially important when pwm dimming is implemented. during pwm off-time the boost converter is not switching. this results in a slow bleeding-off of the output voltage due to leakage currents (i r ). i r , or reverse current, can be a huge contributor especially at high temperatures. on the diode that was selected in this design, the current varies between 1 and 100 a. step 7: choosing the output capacitors. the output capacitors must be chosen such that they can provide filtering for both the boost converter and for the pwm dimming function. the biggest factor that contributes to the size of the output capacitor is pwm dimming frequency and the pwm duty cycle. another major contributor is leakage current (i lk ). this current is the combina- tion of the ovp current sense as well as the reverse current of the switching diode. in this design the pwm dimming frequency is 200 hz and the minimum duty cycle is 1%. typically the voltage variation on the output during pwm dimming must be less than 250 mv (v cout ) so that no audible hum can be heard: i lk = = f pwm v cout = 300 a 5.94 f c out 1 ? d pwm(min) 1 ? 0.01 200 hz 0.250 v (24) a capacitor larger than 5.94 f should be selected due to deg- radation of capacitance at high voltages on the capacitor. two ceramic 4.7 f 50 v capacitors are a good choice to fulfill this requirement. the rms current through the capacitor is given by: i coutrms = 1 ? d (max) d (max) + ? i lused i out 0.960 a 1.67 a 12 = = i in (max) 1 ? 0.745 0.745 + 1.24 a 3.72 a 12 (25) the output capacitor must have a current rating of at least 1.67 a. the output capacitors selected in this design have a combined rms current rating of 2 a. step 8: selection of input capacitor. the input capacitor must be selected such that it provides a good filtering of the input voltage waveform. a good rule of thumb is to set the input voltage ripple ( v in ) to be 1% of the minimum input voltage. the minimum input capacitor requirements are as follows: c in = f sw 1.24 a ? i lused 2.65 f 8 = = ? v in 600 khz 0.1 v 8 (26) the rms current through the capacitor is given by: i inrms = (1 ? d (max)) i out ? i lused 0.363 a 12 = = i in (max) (1 ? 0.765) 0.960 a 1.24 a 3.72 a 12 (27) a good ceramic input capacitor with ratings of 50 v, 4.7 f will suffice for this application. corresponding capacitors include: vendor value part number murata 4.7 f 50 v grm32er71h475ka88l murata 2.2 f 50 v grm31cr71h225ka88l
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 24 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com typical applications designator description part number manufacturer cdd 0.1 f / 10 v grm2195c1h104ja01d murata cdr 0.22 f / 10 v grm188r61a224ka01d murata c in 4.7 f / 50 v grm32er71h475ka88l murata cout 10 f / 50 v grm32er71h475ka88l murata cp 1 f / 16v grm188r61a474k murata cz dnp d1 60 v / 5 a schottky cmsh5-60-ami central semi l1 10 h / 5 a 74477110 wurth electronics q1 nmos fqd13n06ltm faichild r1 100 k digikey rfset 8.45 k 1% riset 12.4 k 1% rovp 732 k 1% r sense 0.015 rz dnp u1 A8508 A8508 allegro the following is the component list for the typical application circuit shown in figure 1.
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 25 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com vdd vdr riset cdd cdr cp rfset mode led5 led7 agnd pgnd pad en gate vin senn senp ovp cout rovp r sense d1 vout v in v c c in c f l1 l2 r2 10 k A8508 led8 led6 led4 led3 led1 led2 pwm r1 fault iset fset/sync comp rvdr vdd vdr riset cdd cdr cp rfset mode led5 led7 agnd pgnd pad en gate vin senn senp ovp cout rovp r sense d1 q1 q2 q3 10 k 1 k vout v in v dr l1 A8508 led8 led6 led4 led3 led1 led2 pwm c in (optional) r1 fault 1 k iset fset/sync comp rvdr application a. typical schematic for boost application with disconnect switch application application b. typical application showing sepic configuration
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 26 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com vdd vdr riset cdd cdr cp1 rfset mode led5 led7 agnd pgnd pad en gate vin senn senp ovp cout rovp r sense d1 q1 vout v in v c c in l1 A8508 (master) A8508 (one slave) led8 led6 led4 led3 led1 led2 pwm r1 fault vdd vdr riset cdd cdr rfset mode led5 led7 agnd pgnd pad en gate vin senn senp ovp rovp vout v in led8 led6 led4 led3 led1 led2 pwm rgate 50 k fault iset fset/sync comp iset fset/sync comp cp2 rvdr rvdr application c. parallel operation of two A8508s; overvoltage protection on master must be set higher than the ovp on the slave vdd vdr riset cdd cdr cp rfset mode led5 led7 agnd pgnd pad en gate hgate vin vsen senn senp ovp cout rovp r sense d1 q1 vout v in v c l1 A8508 led8 led6 led4 led3 led1 led2 pwm radj r1 fault q2 rsc iset fset/sync comp (optional) c in rvdr application d. input disconnect switch configuration for fault protection. option available only in qfn package. contact factory for details.
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 27 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lp, 24-pin tssop with exposed thermal pad contact factory for et and lw packages. a 1.20 max 0.15 0.00 0.30 0.19 0.20 0.09 8o 0o 0.60 0.15 1.00 ref c seating plane c 0.10 24x 0.65 bsc 0.25 bsc 2 1 24 7.800.10 4.400.10 6.400.20 gauge plane seating plane a terminal #1 mark area b for reference only; not for tooling use (reference mo-153 adt) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown b exposed thermal pad (bottom surface); dimensions may vary with device 4.32 nom 3 nom 0.65 6.10 3.00 4.32 1.65 0.45 reference land pattern layout (reference ipc7351 tsop65p640x120-25m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view c c package outline drawing
wide input voltage range, high efficiency 8-channel fault tolerant led driver A8508 28 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com revision history revision current revision date description of revision rev. 1 july 9, 2012 update typical component recommendations copyright ?2011-2012, allegro microsystems, inc. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com

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